However, i am now getting an error saying it is unable to load my data initialization file. Then i tried adding signals from my object window to my wave and running the simulation. on another forum, i found the vsim command, so i tried 'vsim -i top.vhd, ram.vhd' and it simulated successfully! Hi Kaz, thank you! Actually just after posting my reply earlier, i was able to get it to simulate with all the files. You need to make sure you got altera libraries compiles and appear in modelsim list.
If you haven't waveform file you can start with an empty one, then after simulation add nodes to the waves. To run it type in modelsim command window : do file_name.tcl # simulate testbench architecture a, or any file is there some resource that would help me understand how to use these different things?Ĭreate a text file and save with extension. I've only ever modified the waveform directly in quartus and run simulation. I dont have much experience with using tcl or do. However for compile I was able to select multiple files like this and it compiled ok. also if i select multiple files in the simulate option from the toolbar i am getting the same error. so if i simulate just my top level entity file, i get an error saying it cannot find the instance of RAM. Hi Kaz, I am not seeing an option to simulate all the files in the WORK library. Many designers use tcl or do file to compile and run simulation at a single click. The nativelink is not a separate simulator but it launches modelsim from quartus (ready for your design), I never use it. When you compile, check what is the default library. Ideally a testbench can be used to inject data into top level. You will then need to add waveform file by choosing your inputs and applying logic. Then you simulate any level by selecting from work.
In principle you compile any source code into a chosen library which defaults to work. Is it a must that i have to have a test bench? or can i just create/modify waveforms in modelsim to simulate my design? How can i set it up so that i can simulate everything together? if i try to simulate my top.vhdl file, i get an error saying modelsim cant find my work.ram entities. I'm not able to simulate the WORK library itself. However, I'm unable to simulate the design.
In ModelSim, I'm able to compile my design if i select all the files ( VHDL file with my RTL as well as the RAM.vhd which i make using the IP designer ). I want to simulate the design using ModelSim. I have a design of a simple edge detector that instantiates a few RAM blocks ( ALTSYNCRAMs). a lot of it talks about using NativeLink to simulate from within quartus but im ok to use modelsim, since im much more comfortable using the waveform editor. Sorry if this is a very basic question, but i couldnt find the answer in any of the altera documentation. Hi, I'm very new to using FPGAs especially ModelSim(Altera).
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